A CPU must receive data from RAM in the same bit-width as it's internal wiring. A 32-bit processor must receive 32 bits of data from RAM. Memory modules come in various bit-widths (8-bit or 16-bit) and don't always match the bit-width of available processors. To overcome this incompatibility designers have grouped RAM modules into banks that can supply a CPU with its required bit width.

An 8-bit 8086/8088 uses 8 rows of 1-bit-wide RAM to make a bank.
 
A 16-bit 80286 uses 2 rows of 8-bit-wide RAM to make a bank.
 
A 32-bit 80386DX uses 4 rows of 8-bit-wide RAM to make a bank.
 
A 32-bit 80486DX uses 4 rows of 8-bit-wide RAM to make a bank or
1 row of 32-bit-wide RAM to make a bank.
 
A 64-bit Pentium uses 2 rows of 32-bit-wide RAM to make a bank or
one 1 row of 64-bit-wide RAM to make a bank

To calculate the number of RAM modules needed to make one bank, divide the number of data bits per CPU cycle by the bit width of a module.
 

32 bit CPU (internal data bus) / 8-bit-wide SIMM 30 pin = 4 Therefore you need 4 8-bit-wide 30 pin SIMMs to make one bank.

When filling a memory bank in a CPU:

1. Leave the bank completely full or completely empty.
2. First fill bank 0. This may not be necessary on all machines.

NOTE:
All CPU's process information in 8-bit pieces. So, a Pentium which is a 64-bit processor can handle eight pieces of 8 bits each at a time ( 8 x 8-bit = 64-bit ).

There is an important distinction between a memory chip and a memory module as well as the capacity of each. A memory module, also known as a memory stick, consists of a small PCB board and several memory chips soldered to it. A chip has a matrix of cells, each of which holds one bit of data. The amount of information that each chip holds is measured in Megabits (Mb), whereas the amount of information each module holds is usually measured in Megabytes (MB).
 
Memory chips are described in terns of width and depth. A chip with a specification of 256Kb x 1, means it is 256 Kilobits deep and 1 bit wide. To find out how many Megabytes (MB) there are per module ( a module being made up of several chips ), multiply the width x depth x number of chips and divide everything by 8.

30-pin Simm

Depth x Width Kilobits/Megabits	Number of chips per Module	Memory per module Kilobytes/Megabytes
256Kb x 1	8	256KB
256Kb x 4	2	256KB
256Kb x 16	1	512KB
512Kb x 8	1	512KB
1Mb x 1	8	1MB
1Mb x 4	2	1MB
1Mb x 16	1	2MB
2Mb x 8	1	2MB
4Mb x 1	8	4MB
4Mb x 4	2	4MB

 
1 Kilobyte (KB) = 1024 x 8 = 8,192 bits = 8 Kilobits (Kb)
1 Megabyte (MB) = 1024 x 1024 x 8 = 8,388,608 bits = 8 Megabits (Mb)

Error checking technology is not often used for personal computers because of the added cost and the good quality of RAM available on the market. Parity and ECC are two common techniques for error checking. Both the RAM module and the memory controller must use the same error checking method for the system to work.

Data is stored in small 8 bit packages called Bytes. Parity stores error correction information in an extra bit attached to the end of each byte. The value of the ninth bit, or parity bit, is determined in one of two ways.

Odd Parity - If there is an even number of 1's in the byte then the parity bit is 1. If there is an odd number of 1's in the byte then the parity bit is set to 0.
 
Even Parity - If there is an even number of 1's in the byte then the parity bit is 0. If there is an odd number of 1's in the byte then the parity bit is set to 1.

Parity can identify if a single bit has been corrupted with the byte. However, parity checking is limited in that there are many permutations that allow data bits to be changed while maintaining the quantity of ones within the byte to remain odd or even.
 
ECC can correct single bit errors and can detect 2, 3 and 4 bit errors.  

Supports the CPU by governing the flow of information inside the computer.

A trace of parallel wires found on the motherboard.

1. Memory bus - Wires that run from memory controller to RAM.
2. Front Side Bus (FSB) - Bus from CPU to Main memory (RAM)
3. Backside Bus (BSB) - Bus from memory controller to L2 cache.
4. Address Bus - When a CPU requires data it sends a request to the memory controller along the address bus.
5. Data Bus - Data is sent from RAM to the CPU along the data bus.

The wider the address bus the more memory a CPU can access.

Bus Width	Max. Memory
20 bit	1 MB RAM
24 bit	16 MB RAM
32 bit	4 GB RAM

Each data transaction between CPU and memory takes one bus cycle.

Consists of a crystal that pulses at a constant rate when a current is applied to it. These pulses establish a rhythm that synchronizes activities amongst all components on the motherboard. All activity occurs on the positive pulse.
System clock pulses are expressed as square waves where each wave is considered one clock cycle. The pulse count per second usually numbers in the millions and is denoted in Megahertz.

100MHz is 100 million pulses (cycles) per second.

Components need not run at exactly the system clock speed. Most operate at some multiple or division factor slower or faster than the system clock speed.
 

A 500MHz CPU runs five times faster than the 100 MHz motherboard it may be connected to.

FPM (Fast Page Mode)
Data is accessed by addressing the row and column where it resides in memory. Fast Page Mode DRAM eliminates the need to restate the row value if consecutive memory calls access the same row. The reduced overhead improves performance.
 
EDO (Extended Data Out)
Increases performance by assuming that the next data block will be found in a consecutive location in memory. Although this assumption is not always correct, memory access times are decreased by 10% on average.
 
BEDO (Burst Extended Data Out)
Asynchronous access. Each memory request holds 4 data addresses. The first address is processed at the regular 50 ns speed, but since the consecutive addresses are already loaded, access times increase to 10 ns for the following three data blocks.
 
SDRAM (Synchronous Dynamic RAM)
Synchronizes transfers to the system bus speed. PC66, PC100, PC133.
 
ESDRAM (Enhanced SDRAM)
Enhanced SDRAM incorporates a small SRAM cache on the memory module to lower latency and increase burst transfers to 200 MHz.
 
VCM (Virtual Channel Memory)
Virtual Channel Memory can track and fulfill multiple data requests by allocating up to sixteen 1K virtual channels for each bank of memory.
 

VRAM - Video RAM
Dual ported (write and read at the same time). Lower refresh rate then DRAM.
 
WRAM - Windows RAM
Accessible in blocks. Faster than WRAM.
 
SDRAM - Synchronous Dynamic RAM
Single ported. Runs up to 4 times faster than DRAM.
 
MDRAM - Multibank DRAM
Breaks up memory into 32KB banks. Interleaving allows accesses to overlap, increasing performance. Memory size doesn’t affect access time.