PIO modes
Data transfers from hard drive to RAM are controlled by the CPU
Data transfers from hard drive to RAM are controlled by the CPU
PIO Modes
| PIO Mode | MB/s | Standard |
| 0 | 3.3 | ATA-1 |
| 1 | 5.2 | ATA-1 |
| 2 | 8.2 | ATA-1 |
| 3 | 11.1 | ATA-2 |
| 4 | 16.7 | ATA-2 |
| 5 | 33 | Never Implemented |
DMA modes
Single word transfers:
2 bytes (1 word) of data is transferred at a time.
Multi word transfers:
Multiple words are pushed through in a burst per interrupt call.
Single word transfers:
2 bytes (1 word) of data is transferred at a time.
Multi word transfers:
Multiple words are pushed through in a burst per interrupt call.
Hard disk and RAM communicate directly. There were two versions of the DMA implementation. One had the DMA controller located on the motherboard, the other had the DMA controller on the device (Bus Mastering).
Single word transfers
Multi word transfers
Single word transfers
| Single word DMA mode | MB/s | Standard |
| 0 | 2.1 | ATA-1 |
| 1 | 4.2 | ATA-1 |
| 2 | 8.3 | ATA-1 |
Multi word transfers
| Single word DMA mode | MB/s | Standard |
| 0 | 4.2 | ATA-1 |
| 1 | 13.3 | ATA-2 |
| 2 | 16.7 | ATA-2 |
Ultra DMA modes
Ultra DMA implemented:
Two data transfers per clock cycle (on the leading and trailing edge of the strobe signal).Ultra DMA modes
CRC check.
Multiword transfers.
| Ultra DMA mode | MB/s | Standard |
| 0 | 16.7 | ATA/ATAPI-4 |
| 1 | 25 | ATA/ATAPI-4 |
| 2 | 33 | ATA/ATAPI-4 |
| 3 | 44.4 | ATA/ATAPI-5 |
| 4 | 66.6 | ATA/ATAPI-4 |
| 5 | 100 | -- |
32-bit transfers
IDE/ATA transfers data at 16-bits. Enable 32-bit access in the BIOS to take advantage of PCI's 32-bit bus. The hard drive controller will then send two 16-bit chunks at a time.
Block mode transfers
Instead of transferring one sector per interrupt call, Block Mode allows for 16 or 32 sectors to be sent per interrupt.
